December 6 2021: The Indian government has made a total budget allocation for chip design related activities / programmes in the current financial year of Rs. 100 crore (Rs 1 billion).
This was stated in the Rajya Sabha last week, by the Union IT Minister Ashwini Vaishnaw.
He added that currently, semiconductor wafer fabrication facilities for strategic requirements are available at SemiConductor Laboratory (SCL), Mohali; Gallium Arsenide Enabling Technology Centre (GAETEC), Hyderabad and Society for Integrated Circuit Technology and Applied Research (SITAR), Bengaluru.
The Government has approved the following projects for development of semiconductors:
1. The project for “Establishment of Gallium Nitride (GaN) Ecosystem Enabling Centre and Incubator for High Power and High Frequency Electronics” is being implemented by Society for Innovation and Development (SID) under the auspices of Indian Institute of Science (IISc) at Centre for Nano Science and Engineering (CeNSE), Bengaluru at the total project cost of Rs. 298.66 crore.
2. An application for setting up of Assembly, Testing, Marking and Packaging (ATMP) of NAND Flash memory has been approved under the Production Linked Incentive (PLI) Scheme for large scale electronics manufacturing.
3. An application for discrete semiconductor devices, including transistors, diodes, thyristors, etc. and System in Package (SIP) has been approved under the Production Linked Incentive (PLI) Scheme for large scale electronics manufacturing.
Ongoing semicon design efforts
The major on-going initiatives in the area of design of Semiconductors highlighted by the minister in his answer are:
1. Special Manpower Development Programme for Chips to System Design (SMDP-C2SD) was initiated by Ministry of Electronics and Information Technology (MeitY) in year 2014 at 60 academic institutes across the country with an outlay of Rs. 99.72 crore ( Rs 997.2 million0) for duration of 7 years. 150 Application Specific Integrated Circuits (ASICs) have been designed under this programme which are fabricated at Semi-Conductor Laboratory (SCL) and other foundries abroad.
2. MeitY also supports projects at various R&D organizations for incubation as well as design & development of ASICs / System-on-Chips (SoCs) for societal and strategic applications. The major activities taken up for chip design:
- Various state-of the-art ASICs / SoCs such as indigenous Microprocessors, NavIC Receiver, Bluetooth Transceiver, etc., have been designed and developed for societal and strategic applications.
Under the Microprocessor Development Programme, a family of 32-bit / 64-bit SHAKTI, VEGA and AJIT processors have been designed and developed by IIT Madras, C-DAC and IIT Bombay, respectively, using Open Source ISA (Instruction Set Architecture).
- A Fabless Chip Design Incubator (FabCI) has also been setup by MeitY at IIT Hyderabad in year 2016 with an outlay of Rs. 23.73 crore ( Rs 237.3 million) for duration of 5 years for providing design infrastructure, incubation support and technical mentorship to semiconductor design start-ups.
Link to answer tabled in Rajya Sabha