Bangalore, India. June 17 2015: IEEE, has signed an agreement with the Bangalore -based engineering college, Sai Vidya Institute of Technology (SVIT), to offer the IEEE Blended Learning Programme (BLP) in VLSI to all their Undergraduate and Postgraduate students studying Electronics and Communication Engineering (ECE).
The programme will help students build a foundation of VLSI concepts and applied skills for a successful career in the semiconductor industry.
SVIT will provide over 300 students the opportunity to enroll in the VLSI courses. SVIT will work closely with IEEE to establish, on their campus, lab facilities with industry-standard Electronic Design Automation (EDA) tools and other computing infrastructure that meet the guidelines established by IEEE.
The IEEE Blended Learning Program in VLSI is a unique application-oriented training program that aims to increase the availability of skilled engineers in the rapidly growing Electronic System Design & Manufacturing (ESDM) sector in India. The IEEE Blended Learning Programme includes an e-Learning component where students practice and learn concepts in a highly engaging and interactive manner, instructor-led labs, an adaptive assessment, and performance analytics.
Says Prof M.R.Holla, Director and president Trustees, Sai Vidya Institute of Technology: “Our management is determined to foster career opportunities for our engineering students which is why we have decided to offer IEEE’s Blended Learning Programme. These courses will prepare our students for the semiconductor industry and enhance their placement opportunities.”
Adds Harish Mysore, Director-IEEE India Operations:‘’We are excited to significantly expand our relationship with SVIT by offering the IEEE Blended Learning Program to all their students in the Electronics and Communication Engineering department.Through reinforcement of key concepts at every stage and applied project work using the latest EDA tools, these courses will help the students build competency in the field of VLSI and equip them to be successful in their career.”
The IEEE Blended Learning Program in VLSI will commence in August 2015 at SVIT with courses in Logic Design for VLSI Engineers, RTL Verification using Verilog, and Fundamentals of Static Timing Analysis. Each course consists of 10 to 16 hours of e-learning content that students would learn on their own over a period of two to three weeks followed by 2 to 3 days (8 hours each day) of project work in instructor-led labs.
More information here