Bangalore, October 12 2012: Graduate students of the KS Institute of Technology in Bangalore, have created a Fast Fourier Transform (FFT) tool that is both speedier and less power hungry that generally available. They have achieved this by reworking the multiplication module of the FFT processor, effectively reducing power consumption by 60 percent.
Their work has won Karthik.S.Rao, Kathik.C.V and Keshava Koushik.S, the first prize in the Bachelors degree category of the annual Student Design Contest conducted by Electronic Design Automation leader Cadence. The trio were on hand at the just concluded user event, Cadence Live! in Bangalore (October 10-11), to explain their work to many interested professionals. The solution was worked using Cadence tools.
The students were guided in their project by Professor R.Jayagowri.
They have already seen their results published in an international professional journal (DESIGN AND IMPLEMENTATION OF LOW-POWER PIPELINED FFT PROCESSOR; R.Jayagowri, Karthik.S.Rao, Kathik.C.V, Keshava Koushik.S; International journal of VLSI and Signal Processing Applications; Vol 2, Issue 4, ISSN 2231-3133,( 330-335) http://www.ijvspa.net/docs/IJVSPA20120403.pdf
Abstract: The Fast Fourier Transform (FFT) and its inverse (IFFT) are very important algorithms in signal-processing and the most important Orthogonal Frequency Division Multiplexing (OFDM). One key component of OFDM-based systems is the FFT processor which is present in the receiver part. In this paper we implemented the R22SDF pipelined FFT processor using Radix-4 complexity by retaining the Radix-2 butterfly structure with our own designed complex multiplier. The developed architecture is simulated using Cadence tool with 180nm technology. The prize for the Masters degree section of the contest was won by Priyanka Kabara of IIT Bombay for her work: Low Power, Low Noise Signal Conditioning Chip with Differential “Resistance to Frequency” Converter for Resistive Bridge Sensors. Her guide was Prof. Maryam Shojaei Baghini